FALLA=NONE, CLKSEL=PRESCHFPERCLK, RISEA=NONE, MODE=UP, PRESC=DIV1
Control Register
| MODE | Timer Mode 0 (UP): Up-count mode 1 (DOWN): Down-count mode 2 (UPDOWN): Up/down-count mode 3 (QDEC): Quadrature decoder mode |
| SYNC | Timer Start/Stop/Reload Synchronization |
| OSMEN | One-shot Mode Enable |
| QDM | Quadrature Decoder Mode Selection |
| DEBUGRUN | Debug Mode Run Enable |
| DMACLRACT | DMA Request Clear on Active |
| RISEA | Timer Rising Input Edge Action 0 (NONE): No action 1 (START): Start counter without reload 2 (STOP): Stop counter without reload 3 (RELOADSTART): Reload and start counter |
| FALLA | Timer Falling Input Edge Action 0 (NONE): No action 1 (START): Start counter without reload 2 (STOP): Stop counter without reload 3 (RELOADSTART): Reload and start counter |
| X2CNT | 2x Count Mode |
| DISSYNCOUT | Disable Timer From Start/Stop/Reload Other Synchronized Timers |
| CLKSEL | Clock Source Select 0 (PRESCHFPERCLK): Prescaled HFPERCLK 1 (CC1): Compare/Capture Channel 1 Input 2 (TIMEROUF): Timer is clocked by underflow(down-count) or overflow(up-count) in the lower numbered neighbor Timer |
| PRESC | Prescaler Setting 0 (DIV1): The HFPERCLK is undivided 1 (DIV2): The HFPERCLK is divided by 2 2 (DIV4): The HFPERCLK is divided by 4 3 (DIV8): The HFPERCLK is divided by 8 4 (DIV16): The HFPERCLK is divided by 16 5 (DIV32): The HFPERCLK is divided by 32 6 (DIV64): The HFPERCLK is divided by 64 7 (DIV128): The HFPERCLK is divided by 128 8 (DIV256): The HFPERCLK is divided by 256 9 (DIV512): The HFPERCLK is divided by 512 10 (DIV1024): The HFPERCLK is divided by 1024 |
| ATI | Always Track Inputs |
| RSSCOIST | Reload-Start Sets Compare Output Initial State |